1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device.
2. Description of Related Art
A flash memory and an EEPROM (Erasable Programmable Read Only Memory) are known as nonvolatile semiconductor memory devices. A memory cell of such a nonvolatile semiconductor memory device includes a control gate and a floating gate, and stores data by the presence or absence of electrons accumulated in the floating gate.
In order to stably read information stored in a memory cell, a structure is known which incorporates a dummy cell that is identical to the memory cell and uses an output from the dummy cell as a reference (e.g. Japanese Unexamined Patent Publication No. 2004-178621).
FIG. 9 is a circuit structure of the flash memory disclosed in Japanese Unexamined Patent Publication No. 2004-178621. Referring to FIG. 9, a flash memory 30 includes a memory cell 31, a reference cell (dummy cell) 32, control transistors 33 and 34 and a decision amplifier 35.
The symbols Vcc and Vss in FIG. 9 indicate a voltage source potential (generally, 5V) and a ground potential (generally, 0V), respectively.
When the memory cell 31 is selected by a word line, a read voltage Vwl is applied to a control gate of the memory cell 31 through the word line.
The read voltage Vwl being applied to the control gate, a memory cell current Icell corresponding to charges accumulated in a floating gate is output from the memory cell 31.
FIG. 10(A) is a view showing an example of I-V characteristics of the memory cell.
In FIG. 10(A), the I-V characteristics of the memory cell in written mode and the I-V characteristics of the memory cell in erased mode are both shown.
As shown in FIG. 10(A), the memory cell is designed in such a way that there is a sufficient difference between a current Icell1 output from the memory cell in written mode and a current Icell0 output from the memory cell in erased mode when a read voltage is applied.
The memory cell current Icell is supplied to the decision amplifier 35 through the control transistor 33, and information is read by the decision amplifier 35 based on the memory cell current Icell.
The decision amplifier 35 is connected to a bit line 36 and a reference bit line 37, and compares the magnitudes of a current Icell passing through the bit line 36 and a current Iref passing through the reference bit line 37.
The reference cell 32 is used to supply a reference current Iref to the decision amplifier 35.
FIG. 10(B) is view showing an example of I-V characteristics of the reference cell.
The reference cell is set in such a way that the magnitude of the reference current Iref that flows when a voltage Vcc is applied is between the current value Icell1 output from the memory cell in written mode and the current value Icell0 output from the memory cell in erased mode.
Such setting of the reference cell is made by controlling the charges accumulated in the floating gate or the voltage value Vcc applied to the reference cell.
The decision amplifier 35 can determine the data stored in the memory cell 31 by comparing the current Icell passing through the bit line 36 and the current Iref passing through the reference bit line 37.
At this point, a sufficient difference is made between the current value (Icell0, Icell1) output from the memory cell 31 and the reference current Iref, so that a sufficient operating margin is maintained to secure the reading operation.
Because the memory cell 31 and the reference cell 32 have the identical structure, the relative relationship between the I-V characteristics of the memory cell 31 and the I-V characteristics of the reference cell 32 is stable, and normal reading of data is assured.